1. Field of the Invention
The present invention relates to a system having a cache, and more particularly, the present invention relates to a system and a method for cache coherence.
2. Description of the Related Art
In a system with a plurality of access-consumers (processor and peripherals) accessing the same memory, a cache is normally configured in the processor to improve the performance of the system. However, in the case of sharing the memory, it becomes an important subject as how to maintain the coherence of the data in the cache and in the memory.
A directory-based cache coherence system is generally used in the non-broadcasting multiprocessor system. The bit vectors based directory has the capacity in proportion with the size of the entire main memory. The directory is generally static random access memory (SRAM). When the capacity of the main memory increases, the extra cost of the memory to store the directory will become incredibly high. Another optional scheme is using copy tag in each processor cache. However, since the corresponding processor cache tag is temporarily different from the directory tag, when simply using the copy tag, the dirty miss write-back request will be issued first before the miss write-back request is then issued. As a result, the performance of the system will be impaired when dirty miss write-back happens.